Icarus Verilog is a free Verilog simulation and synthesis tool. The CGI program, version 20160328, behind this WWW form provides a simplified interface for compiling and simulating Verilog code using iverilog and vvp. There is even a scrolling textual VCD trace browser; it might not be as pretty as graphical waveform viewers, but it is fairly effective. Even the covered code coverage analyzer is automatically run from this CGI form when a dumpfile is created. A variety of minor restrictions are imposed on the Verilog code, most notably the inability to perform general-purpose file I/O. The only input supported is of Verilog memory files in the VMEM format, which are entered below and read using constructs like $readmemh0(...), etc. The only output supported is of text and a VCD dump, both of which are collected and displayed on this page. This interface is not intended for general use, but was constructed by H. Dietz in Spring 2016 specifically for the use of EE480 students at the University of Kentucky. For that reason, CPU time is limited to 120s and generated file size is limited to 16777216B.
Hello, Verilog user!
The C program that generated this page was written by Hank Dietz using the CGIC library to implement the CGI interface.
Advanced Computer Architecture.